The present invention relates to a process for phasing a local clock, as well as a device for implementing this process, this in the field of systems for receiving data transmitted in digital form, in particular systems using the support medium formed by a television video signal for conveying information coded in digital form, these systems being known under the name "videotext".
It will be recalled that, in this kind of system, messages are transmitted in digital form using a binary code without zero return, by means of data packages coming from one or more sources, each data package being preceded by a burst of identification and synchronization pulses, formed by a succession of alternate 1s and 0s. This burst forms, for the data package which follows, a "heading" intended among other things for identifying the corresponding information source, but its role is also to supply a reference signal, at a given frequency and phase, to which is to be tuned a local clock of the receiver from which the decoding of the message contained in the data package is effected. More particularly, in the "videotext" system considered here, the data packages are inserted in television lines, each package being thus placed between two "line sync" signals usual in television, the technique used being that of time multiplexing of the digital signals with an analog image signal, which allows the existing frequency bands allocated to the broadcasting of television programs to be used. The data packages are thus transmitted over several successive lines or possibly over one isolated line among others containing simply the television image information. For a data package corresponding to a television line, there is inserted, after the "line sync" signal, the synchronization burst then the data package, the duration of said burst being small with respect to that of the data package (in a ratio less than 1/10) and, especially, with respect to the intervals which may separate two successive packages.
The chosen transmission technique requires a demodulation assembly comprising a television receiver associated with an interface system, adapted to be connected to a terminal on which the transmitted message is reconstituted. The interface is formed of a logic part capable of selecting the desired source and a demultiplexing part which retrieves from the video signal the digital information and reshapes it.
It is this demultiplexing part which, in order to reconstitute the data transmitted in packages, includes the local clock and the means for rephasing said clock as a function of the pulses of the burst preceding each data package. It is desirable to synchronize in frequency and in phase an oscillator forming this local clock, during a fraction of the duration of the burst, and then to maintain its frequency and its phase, with sufficient stability, for a considerably longer time, taking into account the above-mentioned relationship between the duration of the burst and that of the data package.
These considerations lead most often to choosing a local clock formed by a very stable oscillator, for example a quartz oscillator, whose frequency is set by construction at a value double that of the pulses of the synchronization burst, this taking into account the choice of coding without zero return. The ideal reading clock is that one whose pulses have active fronts placed in the middle of the 1s and 0s of the synchronization burst. In order to approximate this ideal clock, there is derived from a local oscillator having the desired frequency four clock signals of the same frequency but having phase shifts equal to a quarter of their common period. A stable oscillator may also be used whose frequency is a multiple of the desired clock frequency, and the four clock signals of different phases may be obtained by successive frequency divisions, which comes to the same thing. By phase comparisons, between each of the clock signals and the synchronization burst, the clock signal is determined which presents a minimum phase deviation with respect to the synchronization burst, so the available clock signal having the most favorable phase failing the ideal signal.
This is illustrated by the diagram of FIG. 1 of the enclosed drawings, in which there is shown, from top to bottom:
the synchronization burst S;
the ideal clock pulses HO, having a frequency double that of the burst, and whose rising fronts are exactly centered on the 1s and the 0s of said burst;
the four clock signals H1, H2, H3 and H4 having equal successive phase shifts.
In the example considered, it is clock signal H3 which is selected.
To effect this selection, means have already been proposed for instant phase comparison, comprising flip-flops and a multiplexer, in which a transition of the burst samples two reference phases if four clock signals are available. According as to whether the result is a logic 1 or 0 on each of the two measuring paths of the circuit, it can in theory be determined which of the four available phases is the most favorably placed with respect to the synchronization burst. However it is difficult, in practice, to distinguish a transition of the synchronization burst from a spurious noise pulse. Furthermore, the results obtained are only coherent if the shaped signal, on which this comparison with the available clock phases is effected, presents a strict equality of duration of the 1s and the 0s, i.e. if the taking of the average value giving this signal was perfect, and if this signal does not comprise large random phase fluctuations.
To avoid these disadvantages, it is desirable to compare the local clock phases not with a transition of the synchronization burst but with a state of the bits of said burst, and to average out the result of comparisons made over several bits. To this end, one solution consists in effecting the logic comparison of the signal forming the burst with the signal resulting from the frequency division by 2 of a local clock phase, the average duration of the pulses resulting from this comparison varying proportionally with the phase shift between the two signals. An analog comparison between the result of the preceding operation and predetermined levels could then enable the most favorable clock phase to be selected, particularly by comparing voltage levels.
To illustrate this, FIG. 5 shows, in the form of a simplified diagram, a device belonging to the state of the technique, in which selection is effected between four clock phases H1, H2, H3 and H4. The phase comparison is made between the synchronization burst S and one of the clock phases, for example the one marked H1. To this end, clock phase H1 is brought to a frequency divider by 2, designated by the reference 1, which delivers a signal h1. The bits of burst S and signal h1 are fed respectively to two inputs of a logic "exclusive OR" gate 2, whose output is connected to a low-pass filter 3, formed by an R-C circuit. This circuit delivers a voltage V representing the average value, over several bits of burst S, of the comparison signal obtained at the output of gate 2.
Voltage V is fed to one of the inputs of four comparators 4, which receive also, at their other input, four respective voltage levels V1, V2, V3 and V4, representative of the voltage obtained for the phase shifts corresponding to those of clock phases H1, H2, H3 and H4. The outputs of the comparators are connected to a priority logic 5, associated with a sampling and memorizing stage 6. Finally a multiplexer 7 has its data inputs connected to four available clock signals H1 to H4, and its address inputs connected to the outputs of the sampling and memorization stage 6. At the output of the multiplexer there is delivered the selected clock phase HS, this at the moment when a pulse u appears determining the sampling and memorization of the output signals of comparators 4.
However, the process used by this device comprises an indetermination which is illustrated by the diagrams of FIGS. 2 and 3. In the diagram of FIG. 2, the first three lines are respectively the synchronization burst S, an available local clock phase H1 and the signal h1 resulting from the division of frequency by 2. On the last line are shown the pulses obtained by the combination of signals S and h1 given by the logic "exclusive OR" operation, these pulses forming the comparison signal.
In cases I and II, as illustrated by the arrows and the broken line in FIG. 2, a greater delay of the clock phase h1 with respect to burst S gives rise to an elongation of the pulses of the comparison signal. On the contrary, in case III of FIG. 2, a greater delay of clock phase h1 with respect to burst S gives rise to a narrowing of the pulses of the comparison signal. Comparison of cases I and III, in particular, shows that the results obtained are different, although they correspond to the same phase shift between clock phase H1 and burst S. More generally, it is noted that the direction of variation (elongation or narrowing) is reversed when the phase shift of signal h1 in relation to signal S exceeds the width of a 1 of the burst, which gives two possible values for the voltage obtained representing the average value of the comparison signal, for the same phase shift.
This is illustrated by the diagram of FIG. 3, where there is shown as abscissa the delay .phi. of the clock phase H1 with respect to burst S and as ordinates the average voltage V at the output of the phase comparator. The values and variations of this voltage V, between 0 and a maximum value VM, are indicated for the preceding cases I, II and III. If we accept the special case of a phase shift equal to .pi., it is both the values of voltage V and its direction of variation which are different (compare the straight lines corresponding to cases I-II and to case III).
This disadvantage could be eliminated by conditioning the bringing into service of the divider by 2, giving the signal h1 from clock phase H1, by a determined change of state of signal S (synchronization burst). For example, as soon as the first 1 of this synchronization burst appears, the changes of state of the divider by 2, previously maintained at 0, are enabled. This operation ensures a theoretically determined positioning of the 1s of signal h1 with respect to the 1s of burst S, so as to exclude for example case III previously considered, and so provides a determined direction of variation of voltage V, forming the comparison signal, for an increasing phase shift between signals S and h1.
However, because of the slight inevitable delay of the signal enabling the changes of state of the divider by 2, with respect to the appearance of the first 1 of the burst, and also because of the random phase fluctuations of the fronts of the burst as well as errors of centering of the chopping of the data at the beginning of the burst, there will necessarily exist an indecision concerning the time of enabling the divider by 2, relative to the changes of state of the burst. The result is that, in extreme but not excluded cases, the delay of signal h1 with respect to burst S may exceed the width of a bit of the burst, which results in an erroneous indication V for the clock phase to be selected.
This is made understandable by the diagram of FIG. 4 of the accompanying drawings, in which the upper lines represent the synchronization burst S, the signal z for enabling the divider, and the available clock signal H1 whose phase, with respect to burst S, is close to 0 or 2.pi. (which means that the active front of signal H1 takes place close to a transition of the burst). Division by 2 of clock signal H1 gives then two possible different signals, marked h1 and h'1, and the result is two possible different values at the output of the phase comparator (as illustrated by the hatched zones in the diagram). This serious disadvantage, appearing for phases close to 0 or 2.pi. which are thus the above-mentioned "extreme cases", does not exist for the other intermediate phases, as illustrated by the lower lines of FIG. 4 on which are shown:
clock signal H2 and signal h2 resulting therefrom by division by 2 (phase .pi./2),
clock signal H3 and signal h3 resulting therefrom by division by 2 (phase .pi.),
clock signal H4 and signal h4 resulting therefrom by division by 2 (phase 3.pi./2).
It will be noted, in particular, that the initiation of division by 2 is ensured without difficulty, i.e. without indecision of .pi., if we consider reference clock H3, corresponding to signal h3 shifted by .pi. with respect to the first front of burst S.
The present invention aims at bringing a solution to the whole of the problems outlined above, so as to obtain the most favorable clock phase selection, as much as possible without error, indetermination or indecision.